The present invention relates generally to integrated circuit devices, and more specifically to integrated circuit devices having power on reset circuitry.
Integrated circuit devices often concurrently utilize power on reset (POR) circuitry which provides proper initialization of circuitry upon power up, and special operating modes, which allow for appropriate stressing or testing of an integrated circuit device. Power on reset, typically a pulse, is generated upon power up of the integrated circuit device, and initializes those circuits of the integrated circuit device which require initialization. Referring to FIG. 1, a power on reset pulse is shown. A typical power on reset pulse is a low pulse which transitions to a high logic state when the supply voltage VCC is approximately 2.5 volts. Above this threshold, the power on reset pulse tracks VCC, as shown in FIG. 1.
In addition to power on reset circuitry, special operating modes are frequently invoked in integrated circuit memory devices in order to achieve greater efficiencies in stress testing. For instance, copending U.S. application Ser. No. 08/172,854, titled "Stress Test Mode", filed Dec. 22, 1993, teaches enabling all rows and columns of an integrated circuit memory device simultaneously. While enabling all rows/columns simultaneously is contrary to normal operation, it provides great efficiency in the stress testing of the integrated circuit memory device.
In spite to the benefits represented by power on reset circuitry and special operating modes, their concurrent use may be hazardous. Often, the concurrent use of a power on reset pulse and a special operating mode, such as a stress test mode, may introduce contention problems where the power on reset pulse adversely affects test mode operation. For instance, the power on reset pulse may be attempting to precharge or force a circuit in a direction opposite to the test mode, creating contention between these two signals. If this contention proceeds unchecked, large crowbar currents may result for the duration of the power on reset pulse, which may last longer than 300 uS. The magnitude of these crowbar currents may vary from approximately 100 mA to more than 1A. In addition, the resultant test condition may be incorrect because of the faulty initialization provided by the power on reset pulse.
Thus, there exists an unmet need in the art to be able to concurrently utilize power on reset circuitry and special operating modes of an integrated circuit device without the introduction of destructive contention which causes large crowbar currents.